Die TU Wien will mit Partner_innen aus Wissenschaft, Forschung und Industrie zusammenarbeiten, um die Forschung und Entwicklung von RISC-V-Technologien voranzutreiben.

Als Mitglied der RISC-V-Community wird die TU Wien mit Aktivitäten wie der Mitorganisation des RISC-V Summit Europe und verschiedenen Open-Source-Beiträgen die Community vorantreiben. Die Vision der TU Wien ist es, innovative Anwendungen des RISC-V ISA in verschiedenen Bereichen zu erforschen, einschließlich eingebetteter Systeme, High-Performance Computing und darüber hinaus.

RISC-V ist eine Open-Source-Befehlssatzarchitektur (ISA), die aufgrund ihrer Flexibilität, Skalierbarkeit und Offenheit sowohl in akademischen als auch in industriellen Kreisen großen Anklang gefunden hat. Im Gegensatz zu proprietären ISAs ist RISC-V so konzipiert, dass es erweiterbar ist und es Forschenden und Entwickler_innen ermöglicht, ohne Lizenzbeschränkungen Anpassungen und Innovationen vorzunehmen. Dies macht ihn besonders attraktiv für eine Vielzahl von Anwendungen, von eingebetteten Systemen bis hin zu Hochleistungsrechnern. Infolgedessen fördert RISC-V ein wachsendes Ökosystem, das die gemeinsame Weiterentwicklung von Prozessordesign und Rechentechnologien vorantreibt.

Sowohl das Institut für Computertechnik als auch der Forschungsbereich Embedded Computing Systems haben einen fundierten Hintergrund im Bereich RISC-V und nachweisliche Erfolge in der industriellen Zusammenarbeit. Frühere Arbeiten betrafen Themen wie:

• Schnelle Leistungsmodelle für RISC-V-Prozessoren
• Compiler-Erweiterungen zur Unterstützung benutzerdefinierter Befehlserweiterungen
• Fehlerinjektion und Fehlertoleranzmethoden
• Prozessorerweiterungen im Bereich Sicherheit und EdgeAI-Anwendungen
• Prozessorerweiterungen für Beschleunigungseinheiten

Studierende, Forschungs- und Industriepartner_innen, die an einer Zusammenarbeit zu diesem Thema interessiert sind, können sich gerne an das Institut für Computertechnik oder den Forschungsbereich Embedded Computing Systems wenden.

AGENDA - 1st RISC-V MEETUP AUSTRIA

Feb 25, 2025 14:00 - 19:00
Ort: TU Wien, Karlsplatz, Wien, Seminar Room AE U1 - 5, öffnet eine externe URL in einem neuen Fenster
 

Registration: Not required, we would appreciate a brief notice that you participate, if you not already answered to our outlook invite, by mail to: edeltraud.sommer@tuwien.ac.at

Talk Descriptions:

Herbert Taucher (Siemens): RISC-V in industry – State of the Union

Abstract: This brief overview will analyze the role of RISC-V in industrial applications today and give a perspective into the foreseeable future. Furthermore, USPs of RISC-V will be highlighted, as well as challenges to be addressed. As an active contributor in the RISC-V community Siemens will give a brief summary of relevant activities.

Philipp Tomsich (VRULL): Convergence for Embedded, HPC, and AI/ML: Standards Initiatives for Matrix Processing Instructions in RISC-V

Abstract: The rapid growth of artificial intelligence and machine learning (AI/ML) demands ever-increasing computational performance and energy efficiency. To meet these needs, the RISC-V community has prioritised the standardisation of matrix processing instruction suitable for AI/ML, embedded applications, and HPC. These extensions, developed collaboratively through open standard processes, aim to deliver high performance while maintaining the flexibility and modularity that define RISC-V. This presentation will provide an overview of the two parallel standards track for the Integrated Matrix Extension (IME) and the Attached Matrix Extension (AME), putting these two distinct approaches to matrix processing in RISC-V in context. Attendees will gain insights into the design principles, such as binary portability, scalability, impact on memory models, and software abstractions, that define the solution space explored by these standards efforts.
Bio: Dr. Philipp Tomsich is the Chief Technologist and Founder of VRULL, an engineering consultancy providing strategic software R&D to semiconductor companies building next-generation silicon solutions. He is a seasoned technology leader and industry expert specializing in computer architecture and semiconductor innovation. He drives strategic R&D initiatives in advanced processor design, with a focus on RISC-V architecture and AI acceleration technologies. Dr. Tomsich brings extensive experience in software engineering and system design, complemented by his active contributions to global RISC-V standards and at the RISC-V Technical Steering Committee. A passionate advocate for open standards and collaboration, he is dedicated to advancing cutting-edge solutions for AI/ML workloads across embedded systems and high-performance computing.

Stefan Mangard (TU Graz) - RISC-V Security Research at TU Graz

Abstract: The Institute of Information Security at TU Graz has been working on hardware security for almost 40 years. During the last years, also several security extensions for RISC-V processors have been published. This talk presents an overview of these works based on three different security settings. The first setting assumes that attackers have physical access to the processor and can perform power analysis and fault attacks. We present countermeasures and corresponding verification techniques. The second setting focuses on attackers exploiting memory safety vulnerabilities. We present countermeasures based on encryption and memory tagging. The third setting focuses on establishing trusted execution environments on RISC-V processors. We present approaches for efficient implementations.
Bio: Stefan Mangard is professor and head of the Institute of Information Security at Graz University of Technology. His research interests include hardware security, side channels, cryptographic implementations, security verification, and secure system architectures for application domains ranging from small embedded and IoT devices to cloud solutions. He received an ERC consolidator grant for research on the side-channel security of processors, and he is author of a textbook on power analysis attacks and more than 100 scientific publications. Before joining Graz University of Technology as a professor, he was working as leading security architect at the Chip Card and Security division of Infineon Technologies in Munich. He received his PhD and MSc degree in computer engineering from Graz University of Technology in 2004 and 2002, respectively.

Daniel Große (JKU Linz): Mastering Early System Evaluation and Verification for RISC-V Vector

Abstract: The RISC-V Vector Extension (RVV) enables flexible and scalable vector processing, significantly boosting parallel computation efficiency for AI, HPC, and multimedia by supporting variable-length vector operations and efficient data handling. In this talk, we present the first free- and open-source SystemC TLM based RISC-V Virtual Prototype (VP) with support for RVV Version 1.0. We discuss (a) the integration of RVV and its 600+ instructions in our VP leveraging code generation for over 20k lines of code and (b) our recent optimization techniques to accelerate the Instruction Set Simulator (ISS) achieving up to 406.97 MIPS and a significant average performance increase, by a factor of 8.98 over the original VP and 1.65 over Spike. In the second part, we describe our novel modular, open-source framework RVVTS for positive and negative testing of RVV. At the heart of the framework is our novel Single Instruction Isolation with Code Minimization technique which allows to reduce manual result analysis of failing test cases significantly. By applying RVVTS to the RISC-V VP++ and the QEMU emulator, we confirmed 3 new bugs in the RISC-V VP++ and 2 in QEMU (and 7 more are to be analyzed).
Bio: Daniel Große is a full professor at the Johannes Kepler University Linz, Austria, where he is the head of the Institute for Complex Systems (ICS) as well as the head of the LIT Secure and Correct Systems Lab. His current research interests include verification, virtual prototyping, debugging, synthesis and RISC-V. He published over 170 papers in peer-reviewed journals and conferences in the above areas. Daniel Große served in program committees of numerous conferences, including ASP-DAC, DAC, DATE, ICCAD, CODES+ISSS, GLSVLSI, FDL, ETS, and MEMOCODE and was the General Chair of FDL 2022. He received best paper awards (FDL 2007, DVCon Europe 2018, ICCAD 2018, FDL 2020 and FDL 2022) as well as business-related awards (IKT Innovativ Award 2013, Weconomy Award 2013, and Embedded Award 2014). He is an IEEE Senior Member and an Allied Member of the Accellera Systems Initiative in the SystemC Verification Working Group.

Markus Kobelrausch (TU Wien): A Methodology for Automating the Integration of User-Defined Instructions into RISC-V Systems based on the CV-X-IF Interface

Abstract: With embedded systems and their applications increasing in complexity, there is an ever-growing need for efficient hardware solutions and optimized design methodologies. To tackle that, the OpenHW Group provides a flexible Core-V eXtension interface (CV-X-IF) for utilizing application-specific Custom Instructions (CIs) based on RISC-V. This introduces new challenges as the RISC-V ecosystem requires tools for automating the tedious CI development process. This work proposes a semi-automated flow for integrating CIs into RISC-V processors. The tool utilized in the flow generates a CI-specific wrapper instance based on a generalized template that utilizes the CV-X-IF. In a case study with encryption coprocessors, we found an enhancement in runtime efficiency compared to two software-based algorithms, albeit with a slight increase in the number of cycles per instruction. The reduction in instructions ranges from 68.26% to 88.05%, while the decrease in cycle count ranges from 60.52% to 87.53%, varying based on the eference algorithm being compared. Further, results obtained from expert estimations regarding cryptography-specific use cases indicate a potential time saving of about 64% when compared to manual integration.

Marcus Borrmann (NXP): RISC-V landscape for NXP in Austria

Abstract: As the RISC-V ecosystem becomes more and more important and widely adopted, Europe is investing heavily in this movement as part of its goal to double the share of electronic components design and production by 2030, promoting digital sovereignty and intellectual property autonomy. RISC-V offers significant advantages over proprietary alternatives by enabling customization, enhancing security, and supporting sustainability in processors development with positive return on aspects like safety and security of end applications. NXP in Austria is involved in several European and national public funded initiatives, with various roles to be an active part of the RISC-V movement. The presentation will provide an overview of the current engagements of NXP in Austria and ongoing activities on RISC-V.