The integration of analogue building blocks in modern deep-sub μm and nanometer CMOS technologies, which were developed optimized mainly for digital circuits, enables the realization of complete systems-on-chip (SoCs).

Block diagram of an SoC with antenna, SAW, LNA, mixer, low-pass filter and digital signal processing. The whole circuit is built on a CMOS chip.

© Horst Zimmermann

Example of system-on-chip: radio receiver

For digital signal processing it is necessary to use the newest CMOS technology. This is the reason why also the analogue frontend has to be realized in these state-of-the art technologies.

DC/DC Converters

CMOS integrated MPP tracker with analog power measurement at the PV converter input [Analog Integr. Circ Sig Process 2014]

An integrated converter controller with maximum power point (MPP) regulation in 0.35μm CMOS for photovoltaic (PV) applications is reported. The implemented MPP tracker bases on a perturb and observe algorithm and acquires the information concerning the power flow via an analog processing circuit which is connected at the switched mode converter input respectively the output of the attached PV string of nine cells. There the solar cell current is measured via a very low-ohmic shunt resistor of 1mΩ and analogously multiplied with the cell voltage. As output the fabricated test chip directly generates a 530 kHz PWM signal for the external switched mode converter. Measurements show that under similar conditions analog MPP tracking of the converter input power improves the robustness with respect to settling times of the power path compared to those topologies at which the power is measured at the converter output. Between 0.4 and 7.5 A photocurrent the chip achieves tracking efficiencies better than 99.5 % while the power consumption is only 750μW and a very low chip area demand of 0.043 mm2 for the MPP tracking core is achieved.

Picture of a DC/DC converter chip (three-dimensional)

© Horst Zimmermann



A 40 nm LP CMOS Self-Biased Continuous-Time Comparator with sub-100ps Delay at 1.1V & 1.2mW [ESSCIRC 2013]

A fully differential continuous-time comparator, that consists of a preamplifier-latch cascade, achieves propagation delays of 99 ps for a 50mVpp and 74 ps for a 100mVpp input signal amplitude under 1.1V supply and 1.2mW power consumption. The comparator is completely self-biased thus reducing influence of PVT variations and eliminating the need for a voltage reference. Dynamic delay-power management is supported through digital programmability of the self-biasing and supply voltage scaling. The design occupies 0.0007mm2 in 40 nm LP CMOS process.

Picture of a comparator chip using 40nm CMOS technology.

© Horst Zimmermann

Testchip photomicrograph (2,1mm x 0,77mm)

A 65nm CMOS comparator with modified latch for 7GHz/1.3mW at 1.2V and 700MHz/47μW at 0.6V [ISCC09]

A comparator in a Low-Power CMOS technology (threshold voltage ∼0.4V) is presented, where a conventional latch consisting of two cross-coupled inverters is modified for fast operation, even for low supply voltages, but needing no static current. The sensitivity (BER of 10-9) reached was e.g. for 1.2V 281mV at 7GHz and 27.2mV at 5GHz and at 0.6V 90.2mV at 700MHz and 16mV at 500MHz.

Microphotograph of a comparator with bond wires. The picture has been edited to highlight the comparator, clock driver and output drivers.

© Horst Zimmermann

Microphotograph of 65nm comparator

Measurement graph of the comparator at a clock frequency of 7GHz. The signals shown are: clock signal, test signal, bias signal and output signal.

© Horst Zimmermann

Oscilloscope picture at 7GHz


High-Gain Double-Bulk Mixer in 65 nm CMOS with 830 μW Power Consumption [ETRI 2010, paper of the year award]

A low-power down-sampling mixer in a low-power digital 65 nm CMOS technology is presented. The mixer consumes only 830 μW at 1.2 V supply voltage by combining an NMOS and a PMOS mixer with cascade transistors at the output. The measured gain is (19±1 dB) at frequencies between 100 MHz and 3 GHz. An IIP3 of -5.9 dBm is achieved.

Layoutplot and microphotograph of a mixer using 65nm CMOS technology.

© Horst Zimmermann

Layoutplot of 65nm CMOS mixer

Operational amplifiers

120nm CMOS OPAMP with 690 MHz fT and 128 dB DC gain [ESSCIRC 05]

In this paper an advancement to compensate multistage operational amplifiers is presented. High-gain and high speed operational amplifiers can be realized with this approach. One example of such a high-gain amplifier with a unity-gain frequency of 693 MHz and DC gain of 128.8dB is presented. The high-speed settling is mainly reached by dominant Miller compensation via 4 stages.

Layout plot of an 120nm CMOS op-amp. The image has been edited to highlight elements of the circuit.

© Horst Zimmermann

Layout of the 120nm CMOS op-amp

Analogue filter

A 3rd-Order 235MHz Low-Pass gmC-Filter in 120nm CMOS (ESSCIRC 06)

A 3rd-order continuous-time filter with a cut-off frequency of 235MHz in 120nm CMOS is presented. A linearization technique of an Operational Transconductance Amplifier (OTA) is proposed. The gain of this filter is digitally programmable between 0.5dB and -5dB. The third-harmonic distortion of this filter is –49dB in maximum gain for a 400mV peak-to-peak differential output signal. Two identical filters were implemented on one chip to measure the mismatch which is lower than 0.7 dB in amplitude and 7° in phase.

Schematic of a 3rd-order filter which consists of a series connection of a 2nd order and a 1st order filter.

© Horst Zimmermann

Topology of gmC filter


A 20MS/s 11-bit Digital-to-Analog Converter Using a Combined Capacitor and Resistor Network [NORCHIP 08]

Within this work an 11-bit Digital-to-Analog Converter (DAC) with a combined capacitor and resistor network is presented. The proposed topology contains a series of resistors for the lower 6-bit and a binary-weighted capacitor network for the higher 5-bit. Due to this two-stage design approach, area is reduced by a factor of 12 compared to a simple binary-weighted network requiring 211 unit capacitors. In order to achieve both, high conversion rate plus 11-bit accuracy, additionally to the two-stage design, device matching is improved using a series of two capacitors instead of one for the basic cell. Thus the Differential Non Linearity (DNL) is reduced, as a factor of two in device matching is gained. For the output range of 2.5V to 3.7V a DNL<0.8LSB, an Integral Non Linearity (INL) of 1.68LSB, and a conversion rate of 20MS/s are achieved at a power consumption of ∼8mW at Vcc=5V. The DAC is realized in a 0.6μm BiCMOS process with an active area smaller by a factor of nine compared to the total chip size of 1600x915μm2.

Microphotograph of an 11-bit DAC realized using 0.6µm BiCMOS technology. The size of the DAC is 915µm x 1600µm.

© Horst Zimmermann

Microphotograph of DAC