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Distribudet Algorithms for Robust Tick Synchronization

Future chip technologies are predicted to exhibit higher susceptibility to radiation, leading to an increased rate of bit-flips (“single event upsets”). This also applies for the clock, whose design has become cumbersome in the face of high clock rates anyway. Consequently approaches for tolerating such transient faults are sought.

Andreas Steininger

The DARTS project is dedicated to elaborating a fault-tolerant alternative to the conventional clocking scheme of VLSI-chips, systems-on-chip and other hardware systems. In the traditional approach a single oscillator is employed whose output is distributed throughout the whole system by means of a carefully balanced clock network. Clearly, a fault in this central oscillator or in the clock distribution network causes the whole system to fail. As opposed to this, clocking in DARTS is based on a set of local clock generators that supply several functional regions of the chip individually, thus confining the effect of a fault. In contrast to the classical „Globally-Asynchronous Locally-Synchronous“ (GALS)-approach DARTS does not rely on uncorrelated oscillators as local clock generators but instead employs instances of a distributed algorithm for the fault-tolerant generation of synchronized local clocks. This approach has proven useful in the distributed systems community for decades, however, in context with relatively coarse-grained temporal resolution. The innovation of DARTS consists in the adaptation of such algorithms for the purpose of clocking a VLSI chip. To this end the originally software-based algorithms must be mapped to hardware. Figuring out an efficient mapping that still does not violate the assumptions underlying the formal proofs is a very challenging task.

The researchers (Professor Andreas Steininger) at TU Vienna provide the required expertise on distributed algorithms as well as on self-clocking circuit design, while Austrian Aerospace contributes its experiences in the development of space electronics.
The principal project objective is the development of an ASIC implementing the DARTS algorithm. Experimental measurements on this ASIC shall provide a basis for further optimizations. Austrian Aerospace expects the approach to feature increased robustness of the clock distribution network for next-generation space borne applications, which are exposed to a much higher radiation intensity that causes problems even with current chip technologies.

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For questions contact:
Dr. Andreas Steininger  
Assistant Professor
Institute for Computer Engineering
Vienna University of Technology
Treitlstraße 1-3, 1040 Vienna, Austria
Phone: +43 1 58801 – 18251, -58251
Fax: +43 1 58801 – 18297

Published by:
Daniela Ausserhuber
PR and Communication
Vienna University of Technology
Karlsplatz 13/E011, 1040 Vienna, Austria
Phone: 43 1 58801-41027
Fax: 43 1 58801-41093
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