Supervisor: Prof. Andreas Steininger
Synergies and Conflicts of Security and Dependability from a Microarchitectural Perspective
The correct function of our systems and the security of our data have two fundamentally different opponents: 1. human adversaries, and 2. chaotic, mostly physical processes. This has to some extent driven the predominantly separate development of computer systems in the areas of dependability and security. This is true for academia, where these topics are often discussed by disjoint communities on different conferences, but even more so in industry, where security is often solely seen as a cost factor (and thus minimized) and high dependability is deemed relevant in certain products only. In the design of microarchitectures, however, the reliability issues have become one of the essential
challenges for CPUs manufacturers. Due to shrunk feature sizes the overall soft error rate (SER) of unprotected circuits would lead to dysfunctional systems. These reduced physical margins have also been exploited intentionally to open security holes by corrupting the fundamental expectations on the functionality of the hardware (e.g., Rowhammer and RAMBleed). On the other hand, security is threatened by debatable design decisions that are kept for backward compatibility but also deeply embedded vulnerabilities that might not be recognized for many years. The underlying problem is the increased complexity that creates attack surfaces that are invisible even to experts before they are exploited eventually (e.g., Meltdown and Spectre). Remedies for the resulting effects often have severe drawbacks as they require abstaining from using the procedures developed over multiple decades to enhance performance, latency and/or (energy) efficiency.
By way of our research we want to help to close the gap between dependability and security in the area of computer architecture. More specifically, we want to investigate mutual interactions between hardware provisions that are primarily targeting the improvement of security and dependability, respectively. To that end, we need to improve on the state of the art techniques for fault injection and co-emulation of CPUs. Based on that, we plan to propose improvements to make the provisions work more tightly together to reduce the overall complexity (influencing power, speed, area).